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Figure 8.9
Illustrating four types of consistency [3]. (a)
Sequential consistency: LD and ST follow program
order. (b) Processor consistency: LD may precede
buffered ST, other processors may see differing
order of {ST, LD} access. (c) Weak consistency:
synch operations are sequentially consistent; other
memory operations {M,M} can occur in any order.
(d) Release consistency: synch operations are split
into acquire(lock) and release(unlock), and these
operations are processor consistent. |
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of actions. Goodman [108] developed a less restrictive form of consistency called processor consistency (Figure 8.9b). The issuing processor sees sequences of loads or stores, or loads followed by a store to be performed in program order. But a store followed by a load is not necessarily performed in program order, nor is any sequence of memory operations as observed by another processor performed in program order. Allowing loads to precede stores as performed merely recognizes that many machines use store buffers. Allowing unpredictable sequences of memory operations requires observer processors to be explicitly synchronized by the programmer when using shared data. |
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Dubois et al. [79] introduced a notion of weak ordering or weak consistency that has been refined by Adve and Hill. Their definition was that a system is weakly ordered with respect to a synchronization model if and only if it appears sequentially consistent to all executions of a program that obey the synchronization model (Figure 8.9c). In practice, a program obeys the synchronization model if and only if: |
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1. All synchronization operations must be performed before any subsequent memory operation can be performed. |
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2. All pending memory operations are performed before any synchronization operation is performed. |
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3. Synchronization operations are sequentially consistent. |
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We now need to know that the various outstanding memory operations are complete. To do this, we introduce a new operation called a fence [42, 253]. This operation precedes a synchronization operation and ensures that the outstanding memory operations are performed. |
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An even weaker consistency model has been developed by Gharachorloo [101] called release consistency (Figure 8.9d). Here the synchronization |
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