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13. If a set of shadow registers, RS1, RS2, RS3, RS4 were available, how could the code in problem 9 be restructured to minimize dependencies? Show the new M1. |
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14. Using the assumptions of study 7.1, time out the code in problem 9 for |
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(a) Control flow (improved). |
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(b) Dataflow (with value-holding reservation stations). |
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(c) Control flow with shadow registers. |
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15. How would the dataflow timing change in study 7.1 if all three instructions were issued in the same cycle? |
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16. Repeat problem 15 for the improved scoreboard, again using the functional unit timing of study 7.1. |
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17. A certain vector processor has a memory buffer that does not allow reconfiguration (each TBF/m is a separate buffer). How does this affect the overall overflow probability? |
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18. Using the baseline area assumptions of Chapters 2,4, and this chapter, estimate the overall area (f = 0.75) of a dual-issue superscalar processor with 8KB I-cache and 8KB D-cache. Assume double-sized ALU to accommodate execution. State all assumptions and show functional area allocation. |
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