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Page 500 EXAMPLE 7.9 MULTIPORTED REGISTER AREA Compute the area for the register sets. 1. A multi-issue processor with 32 ´ 64 register bits and 8 ports. Area = (32 + 3(8)(64 + 3(8)) = 4928rbe. 2. A vector processor with 8 registers, each of 64 elements, each element having 64 bits. The vector registers support 8 ports. Area (register only) = 8 ´ [ (64 + 6) (64 + 6) ] = 39,200rbe Area (switch) = 2(64)(8)(8) = 8,192rbe Area total = 47,392rbe. 3. This results in an area difference of 47,392 - 4,928 = 42,464rbe required to support the vector registers. Note that from the preceding example, the difference (42,64 rbe), is a significant amount of processor areaas we recall from studies on our baseline processor, exceeding the probable area of the floating-point units themselves. Another way of viewing the additional vector register area is to compare it to an equivalent amount of data cache. The additional vector register area would correspond to about 70,800 cache bits (at 0.6 rbe per cache bit), or somewhat less than 8 KB of data cache. Recall that vector processors in general have a small data cache or buffer to contain scalar data values, but the multiple-issue machine will surely require a considerably Figure 7.54 Memory size vs. entries per chip for various interleave factors (m), assuming memory word = 8 bytes. Chip size is number of memory words per chip (e.g., 4M ´ 4b has chip size of 4M entries ).
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