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2. Much of the available concurrency can be realized with relatively small window sizes (about eight). |
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3. When the execution pipeline is long (relatively slow floating-point execution, etc.), the advantage of multiple-instruction execution is greatly diminished. |
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4. Out-of-order execution, at least for most of the models studied, offers an improvement over in-order execution of about 20%. |
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5. Windowed out-of-order execution, dispatching one instruction per cycle (M = 1), affords an additional 20% performance advantage. |
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It is becoming increasingly fashionable among computer marketing agents to cite the maximum number of instructions that can be simultaneously issued by a processor as a basic measure of processor performance. After all, a machine that can issue 5 instructions per cycle ought to be 5 times faster than a machine that issues only one instruction per cycle. |
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At least, it would seem that way. In assessing the performance potential, the careful observer will consider obvious resource limitations. For example, are there ports and busses enough to support four updates to the register set each cycle? |
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Ordering restrictions: is there support for out-of-order instruction execution? There is a fine point here, and essentially it is this: must load and store instructions execute in order? After all, these are the most common instructions by frequency. These are also the instructions most likely to create interrupts or faults due to memory management considerations. Regardless of what the marketing brochure says, if the processor does not have reordering hardware (history registers, etc.) and requires in-order execution of instructions that access memory, its overall behavior will resemble that of a machine that executes all instructions in order. There will be rather little advantage from the multiple-issue hardware. |
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Speculative execution: if the processor truly supports out-of-order instruction execution, does it support speculative execution (i.e., execution of code beyond the conditional branch)? Speculative execution can enhance processor speedup, possibly by up to 50%. |
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Typically, details on instruction ordering restrictions and speculative execution restrictions are not the kind of information generally provided when a processor is first introduced. The more complex the processor, the more certainly its effectiveness can be understood only by thorough understanding of its detailed organization and limitations. |
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