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Page 474
For the dataflow approach with reservation stations that hold values, we might have the following:
Cycle 1
Decoder issues I1®DIV unit
R1
®DIV Res Stn
R2
®DIV Res Stn
TAG_DIV® R3
Cycle 2
Begin DIV.F
Decoder issues I2®MPY unit
TAG_DIV®MPY unit
R4®MPY Res Stn
TAG_MPY®R5
Cycle 3
Multiplier waits
Decoder issues I
3®ADD unit
R6®ADD Res Stn
R7®ADD Res Stn
TAG_ADD®R4
Cycle 4
Begin ADD.F
Cycle 6
ADD unit requests broadcast next cycle (granted).
ADD unit completes this cycle.
Cycle 7
ADD unit resutl ®R4
Cycle 9
DIV unit requests broadcast next cycle (granted).
DIV unit completes this cycle.
Cycle 10
DIV unit ®R3
DIV
unit ®MPY unit
Cycle 11
Begin MPY.F
Cycle 14
Multiply completes and requests data broadcast (granted).
Cycle 15
MPY unit result ®R5.

In the preceding timings, the control details did not concern us; the timing difference arose from the use of reservation stations that hold values in the second implementation. This allowed the ADD.F instruction to proceed because the old value of R4 had already been transmitted to the multiplier.
While the savings of one cycle in this example may not appear very significant, the ADD.F instruction completed in cycle 7. Any instructions dependent on the ADD.F could then proceeda speedup of more than twice for those instructions.
As far as implementation is concerned, the issue logic is now distributed in the reservation stations. If multiple instructions are to be issued in the same cycle, then there must be multiple separate buses to transmit the information: operation, tag/value #1, tag/value #2, and destination. With dataflow, we assume that the reservation stations are associated with the functional units. If we centralized the reservation stations for implementation convenience, the design would be generally similar to an improved control flow, or scoreboard, described in the next section.
Action Summary
We can summarize the basic rules for any processor (dataflow or improved scoreboard, discussed next) that has reservation stations that hold values:

 
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