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1. Low-order interleaving of multiple memory modules. |
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2. Fast sequential page mode within a module. |
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These two techniques can be combined as necessary to afford even higher memory bandwidth. |
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Accessing multiple memory modules can result in conflicts that reduce the available memory bandwidth to something less than that offered. The now-classic problem of modeling the conflicts that arise when n uniformly distributed address requests are made to m independent memory modules has been well-studied. Generally these modeling studies give the same result for m,n ³ 4. Moreover, any actual processor, and certainly all pipelined processors as outlined in this text, will not correspond to the ideal processor making exactly n uniformly distributed requests each memory cycle. Thus, an approximate solution is quite adequate for performance analysis purposes. |
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For purposes of this book, queue-based models are preferred for describing memory contention and processor memory interaction. While for large m,n they generally give the same result as other models, they have at least two advantages: |
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1. They are robust enough to describe complex processors that make references to memory under a probability distribution. |
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2. They are the basis for an analysis of many other computing systems issues, such as multiprocessor memory interaction and concurrent I/O. |
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For many cache-based processors, memory contention is eliminated, as the processor ceases action until the memory system handles the cache miss. For simple copyback caches, memory contention can be ignored unless the I/O traffic becomes significant. Processors with write-through caches may notice some performance degradation due to write memory traffic contention. |
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In the longer term, simple uniprocessors with cache are unlikely to be a primary focus of designers. Hence, robust memory models are a requirement for understanding complex processor-memory behavior. We shall see more of these in chapters 7 and 9. |
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6.10 Some Areas for Further Research |
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Memory systems design is broadly limited by technology, data integrity, and accurate multihierarchical models. While technological issues are generally beyond the research interests of most readers, issues such as the tradeoff between access time, capacity, and chip organization (e.g., 1MB´ 4B vs. 4MB´ 1B) are generally not well understood. Increasingly, the problem with memory technology is not the memory chip itself, but rather the buses (data and address) that connect the processor to the multiple memory chips. The bandwidth and access time and latency on these buses frequently determine the basic performance limits of the memory system. |
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