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address resolution is to the byte. In order to maintain a bit-efficient instruction layout in memory, processors adopt an offset + base (offset[RB]) address format. The base value contained in RB defines the starting point of a region of user memory. Within this region, items are addressed by the offset. Indexing and literal facilities also reduce cache size, providing for offset[RB, RX] or #value. Index values contained in RX usually represent a dimension of the data structure underlying the data being processed. Often these offsets are adjusted by multiplying by the reference size, as in an array subscript. This is relatively fast, as this multiplication is typically a power of 2 and may be performed using a shift instead of an actual multiplication. We assume our processors have these facilities without concerning ourselves with the details of how they are specified (i.e., the bit allocation) in the instruction layout. |
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The Curse of Register Modes! |
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Register modes provide an orderly arrangement for specifying the use of a register. They were regarded as a significant improvement in minicomputer instruction set design when introduced in 1967 by DEC in the PDP-11. |
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They can have an unfortunate consequence for pipelined processor designs, however, especially when the size of the instruction being executed depends on the specified mode. Here the starting point of the next instruction or even the next operand is unknown until both the opcode and subsequently the register mode are decoded. |
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This significantly complicates the advanced fetching and alignment of yet-to-be-executed instructions. |
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Often (especially in R+M processors) extended address facilities are made available in the instruction by the use of address mode bits. An elaborate set mode bit is found in VAX (see Table 1.17) and M680x0 family processors. As not all modes are used with the same frequency, various mode subsets or other arrangements (encoding mode information in the opcode or including special mode bytes) have also been popular. |
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1.6.2 System Addresses and Segmentation |
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Most modern system applications require the cooperation of multiple independently written programs (processes). Each process must be relocated and protected with respect to other processes to insure both correct operation and that errant processes are restricted to their own scope. |
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The basic mechanism usually employed to accomplish this is a segmented address space. The overall address space is broken up into units (segments), each with its own base and bound register (Figure 1.20). The operating system (itself operating in a segment) manages the collection of these registers (sometimes called control registers). The upper bits of the user (process) address can be used to address different segments. A typical segmented address computation is shown in Figure 1.21. The upper process address (6 to 8 bits) addresses a segment table (in registers or memory). The base |
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