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(c) Regularthis pattern arises from vector or array references and corresponds to an access pattern wherein each access is separated by a fixed number of addresses. |
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Purely sequential reference behavior arises from certain types of cache accessing main memory (copyback cache). The random request pattern is commonly used in memory systems evaluation for the design of general-purpose processors with or without cache, so long as copy-back cache is not used. Regular reference pattern is used in the design of certain high-performance vector processors. For purposes of this chapter, we shall be concerned only with sequential and random address patterns. |
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5. Evaluation of the memory model. This step is the primary analytic evaluation of the proposed memory partition as measured against the processing requirements. The evaluation of the memory system model provides an assessment of the achieved bandwidth, the actual memory access time (including contention), and the queueing required in the memory system in order to support the achieved bandwidth. |
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6.3.2 Models of Multiple Simple Processors and Memory |
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In order to develop realistic memory models we need a more detailed model of the processor. Frequently, we model a single processor as an ensemble of multiple simple processors. Each simple processor issues a request as soon as its previous request has been satisfied. Under this model, we can vary the number of processors and the number of memory modules and maintain the address request/data supply equilibrium. While this is valuable from a modeling point of view, these configurations pose difficulties in interpretation to the designer of a single high-speed processor with known peak request rate. As a first approximation in order to convert the single processor model into an equivalent multiple processor, the designer must determine the number of requests to the memory module per module service time, Ts, = Tc. If a certain processor has a peak request rate of 10 million accesses per second and the memory module has cycle time Tc = 1 ms, then the processor acts as if it were 10 processors, each requesting a single item of service from memory each memory cycle. |
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The nature of the processor is very important here. A simple processor makes a single request and waits for a response from memory. A pipelined processor makes multiple requests for various buffers before waiting for a memory response. Thus, the equivalence of n simple processors, each requesting once every Ts, and one pipelined processor making n requests every Ts (Figure 6.11) is only approximate. As we shall see, machines with buffering mechanisms and/or cache-organized memories have behavior different from multiple simple processors with equivalent memory traffic. |
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In the following discussion, we use two symbols to represent the bandwidth available from the memory system (the achieved bandwidth): |
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1. B: the number of requests that are serviced each Ts. Occasionally, we also specify the arguments that B takes on, e.g., B(m,n) or B(m). |
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2. Bw: the number of requests that are serviced per second: Bw = B/Ts. |
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