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Figure 6.10
Module addressing. |
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the lower bits of the address define a word in that module. |
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In lower-order interleaving, the lowest bits are used to address a memory module within the memory system. Then the upper bits define an address for the word to be retrieved from the particular module and forwarded to the processor. In higher-order interleaving, most of the requests (by the locality principle) tend to remain in a particular module, at least over a short period of time, whereas in low-order interleaving the requests tend to be distributed across all of the modules. High-order interleaving is sometimes useful in memory systems design for increasing the reliability of the memory system. Given a failure in a low-order interleaved memory system, processing must cease, as it is very likely that a request will be shortly forthcoming directed at this damaged memory. On the other hand, with high-order interleaving the system can be reconfigured; that is, reconstituted to accommodate at least those applications that are small enough to fit in an undamaged part of memory. With additional control complexity a low-order interleaved memory system can also be reconfigured to a smaller memory size to allow continued processing. |
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6.3 Models of Simple Processor-Memory Interaction |
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The basic issue in modeling the memory system, given a collection of m modules each with cycle time Tc, access time Ta, and a certain processor request rate, is: how do we model the bandwidth available from these memory modules, and how do we compute the overall effective access time? Clearly, the modules in low-order interleave are the only ones that can contribute to the bandwidth, and hence they determine the factor m. From the memory system's point of view, it really does not matter whether the processor system consists of n processors, each making one request every memory cycle (i.e., one per Tc), or one processor with n requests per Tc, so long as the statistical distribution of the requests remains the same. Thus, to a first approximation, the analysis of the memory system is equally applicable to the multiprocessor system or the higher-speed pipelined processor. The request rate, defined as n requests per Tc, is called the offered request rate, and it represents the peak demand that the non-cached processor system has on the main memory system. |
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