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entry: LD.W R1, xCounter ;get x size from memory
LD.W R2, xBaseAddress ;get the base value
CLR.W xSumAddress ;initialize sum to 0
loop: ADD.W xSumAddress, [R2++] ;add next element to sum
BCT.NE R1, loop ;and continue until done
END |
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There is an instruction to load an address into a register (LD .W), an instruction to clear a memory location (CLR. W), an instruction that decrements a register and branches if not zero (BCT. NE), and an instruction with an an addressing mode that uses a register as an index value and then increments it by the appropriate amount based on the data type specified. However, there are other considerations in machine design that make the R+M approach less attractive. For example, in order to perform these instructions without penalty, an additional adder might be required to perform the address increment without conflicting with other instructions (such as the following BCT. NE instruction, which performs both a subtract (by one word size) and an effective address calculation). Thus, the actual utility of such an instruction (although common in many machines) must be considered on a case-by-case basis. |
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Several final simplifications should be noted. First, there is no use of BC. T this is used sparingly in this text, as statistically it is an uncommon instruction. Second, there is no consideration whether the branch to loop is relative to the program counter or absolute (relative to some special base register). Code that references absolute addresses must always be run at exactly the same locations and may therefore be less versatile. Either of these alternatives could expand the address modes specified in Table 1.15. Third, no detailed consideration of condition codes is made. It is assumed that appropriate condition codes are used. The timing of condition code12 setting is extremely important for program branching, as we shall also see. |
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1.5.7 Other Instruction Set Issues |
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System States and Sequencing |
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Rather than distribute various pieces of control information throughout the processor, modern instruction sets tend to collect them into a single program status word (PSW), thus facilitating change of control operations (supervisor calli.e., call to the operating systeminterrupt, etc.). |
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The PSW (Figure 1.16) usually includes both user-defined control information, such as: |
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1. Condition code: defining whether the result of the preceding instruction was = 0, > 0, < 0, or overflow. |
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2. Current instruction address (if not, as in VAX, in a specified register). |
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12Some of the first "RISC" machines did away with condition codes entirelythe sole conditional branch mechanism was to test a register for 0 (very fast to implement) and then to provide a collection of test and set instructions to store the truth or falsity in a destination register. This has become less common as other hardware and software techniques have increased the performance of branches without eliminating condition codes. |
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