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Figure 5.29
Design target miss rate of data cache (fully associative,
demand fetch, fetch on write, copyback with LRU
replacement). |
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Figure 5.30
Split cache management. |
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1. Duplicate lines : If miss on I-reference, memory line goes to I-cache. |
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If miss on D-reference, memory line goes to D-cache. |
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On CPU store reference check both directories: |
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Use write policy in D-cache; |
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Invalidate line in I-cache. |
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2. No duplicate lines: If miss on I reference, memory line goes to I-cache
and check D-cache directory; invalidate if present. |
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If miss on D referenc, memory line goes to D-cache
and check I-cache directory; invalidate if found. |
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On CPU store difference check both directories. |
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