|
|
|
|
|
|
|
Figure 5.21
Interference of system references. |
|
|
|
|
|
|
|
|
FIFO amplifies the LRU miss rate (DTMR) by 1.12 (i.e., 12%) on the average [259]. |
|
|
|
|
|
|
|
|
While LRU is the best-performing replacement algorithm, it does involve additional hardware control and complexity. For two-way set associativity, only one extra directory bit is required for directory entry. This bit is then toggled to indicate which of the entries was last accessed. As the degree of associativity increases, the number of "history" bits also increases [259]. For an m-way set associative memory, (m - 1) log2 m bits are required per directory entry. This represents not only directory cost (in bits) but significant additional control to manage the update process. This cost can be reduced by various mechanisms that approximate LRU performance. |
|
|
|
|
|
|
|
|
5.8 Cache Environment: Effects of System, Transactions and Multiprogramming |
|
|
|
|
|
|
|
|
Most available cache data is based upon trace studies of user applications. It is from this environment that our DTMR figures have been derived. Actual applications are run in the context of the system. The operating system tends to slightly increase the miss rate experienced by a user program; Agarwal [4] has studied this for the VMS operating system. Figure 5.21 shows the results of his study. The system itself contributes 20% of the miss rate over a broad spectrum of cache sizes. Another 10%20%, roughly, is attributable to system-user interference. The data in this figure is derived from the assumption that the user program runs through to completion, and calls upon the system only for those services required for its execution. We can adjust the DTMR from Figure 5.10 by including the effect of the system for a single user process running through to completion, which can be seen in Figure 5.22. |
|
|
|
|
|
|
|
|
Multiprogramming environments (especially extended multiprogramming transaction environments) create special demands on a cache. Caches in |
|
|
|
|
|
