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Figure 5.19
Line access strategies. |
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1. Slow, mininizes cache control (access and fill): |
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Reference to a line always starts on a line boundary in memory. CPU does not resume untill entire line is placed in cache. |
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2. Fast, or minimum miss time (fetch bypass): |
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First reference to memory is to the faulted (missed) word. This is forwarded directly to the CPU (and simultaneously to the cache) and processing resumes. The remainder of the line is loaded into the cache as the CPU activity allows. |
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3. Various intermediate strategies are possible. |
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4. Nonblocking caches wherein the processor continues execution so long as the execution does not directly depend on or use the cache data to be fetched. |
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