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Software Practices and Benchmarking |
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Designers try to understand their environment by sampling benchmarks that they believe to be representative of their environment and, at the same time, somewhat control the future usage of the machines by controlling software practices. Depending upon the breadth of benchmarks used in preparing the design, the resultant processor may be very sensitive to particular aspects of new benchmarks [185]. A large and robust sample set of user programs is invaluable in assessing many issues in processor design. This suite of test programs forms the basis of the design process, the basic data and information upon which the design will be based. |
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In the marketplace, however, users choose their own benchmarks that may or may not have already been considered in the design process. Almost every design team will consider all of the well-known widely available benchmarks in making design decisions. Until the advent of SPEC marks, these better-known benchmarks did not come in a single standardized version, nor were they maintained by some independent agency. They frequently underwent change, modification, and extension. |
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Yes, Gentle Reader. It has not been unknown for vendors to modify a well-known benchmark and quietly introduce it into the user community. The purpose of the modification may not be particularly to show one's own product at great advantage, but rather to demonstrate a particular "killing flaw" in a rival's product offering. |
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higher clock rates. For the moment, we assume the processor uses a guess in-line branch prediction. |
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From Chapter 3, the relevant instruction frequency profile derived from Tables 3.4 and 3.143.15 is as shown in Table 4.19. |
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The branch profile is: BR = 2.6%, BC = 10.4%, BC that go to target 54%. |
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We evaluate the BR penalty as: |
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The delay due to BC can be determined: |
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Since the CC is set by the end of EX, there is no penalty when the BC goes in line. If the BC goes to the target, the situation is the same as the BR casea 2-cycle penalty. |
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