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the cache pipeline segments in the same order. For example, the ST may update the cache directory in the cycle following its initial access to an entry. This could be the same cycle required for a fetch by the next instruction, requiring a one-cycle delay. |
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Suppose that in the previous example, the divide execution took six cycles, and each division had to be serially executed (i.e., no pipelining within the divider). Then, if we had the following sequence: |
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DIV R1, ALPHA[]
DIV R2, R3 |
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the following penalty might ensue: |
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A similar situation arises with the "run-on" delays; the instruction following the divide must be delayed, even if it does not depend in any other way on the divide. This ensures in-order execution. Thus, |
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While divide itself is infrequent in typical code, clustered arithmetic operations using the same function are not unusual. Thus, processor resources must be carefully designed to accommodate peak rates. |
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Data dependencies (case 3) and resource dependencies (case 5) create obvious pipeline breaks or delays with no out-of-order execution, and even if out-of-order execution were allowed, they significantly aggravate delays due to conditional branch. Case 3 is a good example; suppose * - 2 is an add instruction whose result is to be placed in R1. Now, instruction * - 1 is a multiply instruction (with 6-cycle execution), one of the components of which lies in R1; thus, the operand for the multiplier cannot be determined until * - 2 is completely executed. If a BC instruction lies at *, then * + 1 is delayed by 10 cycles over its scheduled decode time. Similar situations arise with resource dependencies. |
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The next three studies concern a hypothetical R/M machine that uses a single 32-bit instruction format. This is a hybrid machine between our L/S and R/M machines. In the first study, we look at dependencies that arise in a sequence of five instructions. We look at both the individual dependencies as they arise |
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