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Chapter 4
Pipelined Processor Design |
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This chapter discusses the design of pipelined processors. A processor is designed as several different levels, each with increasing design detail. In this chapter we discuss high level or the architectural level. This serves as the specification for the logic design and implementation levels. Even at this high level a large number of decisions need to be made, each of which involves evaluating the relative cost and performance of a set of design alternatives. Here, we present such alternatives as they apply to the central processor, or CPU. Memory performance enhancements such as caching and interleaving are discussed in later chapters, and therefore are considered here only insofar as they directly affect CPU design. |
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Of course, every processor design begins with a set of market objectives. Commercial manufacturers usually envision a range of products: from those with low performance and low cost to those targeted for very high performance where cost is a secondary consideration. An entry product might have a target of 10 MIPS (million instructions per second). Other products could have targets of several hundred MIPS, with a price perhaps 1020 times that of the entry system. This range of products necessitates a whole series of different design decisions to meet the market objectives. Two fundamental elements of the decision process are the characteristics of the technology to be used and the organization of the machine. The technology choices often seem overwhelming: BiCMOS, CMOS, CML, ECL; each implemented in gate array, standard cell, or custom parts and packaged in a single-chip package or on multichip carriers. We assume that the ''right" technology choices for the product have been made, and that an efficient (in some cost-performance sense) fundamental cycle time for the machine has been determined, based on the number of levels of logic in critical paths, the speed of each level of logic, and the time required for signals to propagate between levels. Now a machine organization must be designed that is appropriate to the technology and achieves the cost-performance goals. |
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