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Design Target Data and Tools Used in This Chapter |
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1. Based on the data in Tables 3.2 and 3.3, compute the expected instruction bandwidth for R/M and R+M architectures relative to L/S. The instruction bandwidth is the number of instruction bits required to execute a program (e.g., suppose a program consists of 100 HLL operations). |
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2. For an R/M machine, suppose all instructions but the LDM and STM execute in unit time. If the LDM and STM require a number of time units equal to the number of registers moved less one (i.e., the excess over a simple LD or ST), compute the effect of LDM and STM on performance. Use mean LDM/STM data from section 3.3.1 and Table 3.15. |
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3. What percentage of branch instructions have generally predictable outcomes (greater than 90%)? For both scientific and commercial environments, make a table of branch instruction types. Specify the probable outcome and whether the outcome is predictable to greater than 90%. |
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