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| Table 3.18 Register use for effective address calculation in various programs. | | Range | | | | | | | | | Max.** | | | | | Min.** | | | | | Avg. | | | | | **Max/min refers to the program that makes maximum/minimum use of registers in address calculation. | | *Excluding scientific object code, the usage would be max = 8% and average = 4.3%. |
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where R1, RX, and RB designate three general-purpose registers. Now suppose we have the sequence: |
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LD R4,
ADD R7, DISP [R5, R4] |
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We are unable to generate the operand address for the ADD until the LD is completed, as the value in R4 is unknown until then. The destination of the LD instruction may be either the index register or base register, creating an address generation dependency. If the destination were a source operand (in the ADD R7,) then we would have an execution dependency. Address and execution dependencies occur in L/S architectures in similar ways; e.g., |
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LD R4,
LD R7, DISP [R5, R4] |
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The second LD instruction must await the completion of the first instruction before it can complete its address generation. |
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Address Generation Dependencies |
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An address generation dependency occurs when the result register of one instruction is used as an index or base register by a following instruction. Address generation delay is determined by the distance (number of instructions) between instructions that set a particular register and the instruction that uses it in generating addresses. The distance is weighted by the corresponding delay, e.g., a distance of one could cause a corresponding delay of two, while a distance of two would have a delay of one; distances beyond two would have no delay. The greater the distance the less the effect. Table 3.19 shows the address interlock distances for a scientific environment. |
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An execution dependency occurs when the result register of one instruction is an operand register of a following instruction. The effective execute interlock delay is also determined by the distance between the instruction |
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