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Table 3.15 Expected distribution (per 100 HLL operations) within Move class of instructions (scientific applications) by architecture type.
L/S
R/M
R+M
Integer Load (LD)
36
(34%)
24
(28%)
11
(41%)
Integer Store (ST)
16
(15%)
13
(15%)
6
(22%)
Floating Point Load (LD.F)
23
(21%)
17
(20%)
2
(7%)
Floating Point Store (ST.F)
18
(17%)
16
(18%)
1
(4%)
Integer Register Move (MOVE)
10
(9%)
12
(14%)
3
(11%)
Floating Pt. Register Move (MOVE.F)
2
(2%)
3
(3%)
2
(7%)
Load Multiple Registers (LDM)
1
(1%)
1
(1%)
1
(4%)
Store Multiple Registers (STM)
1
(1%)
1
(1%)
1
(4%)
Total
107
(100%)
87
(100%)
27
(100%)

Table 3.16 Expected distribution (per 100 HLL operations) within Move class of instructions (commercial applications) by architecture type.
L/S
R/M and R+M
Integer Load (LD)
54
(12%)
18
(41%)
Integer Store (ST)
16
(4%)
5
(11%)
Memory-to-memory Move (MOVE.C)
364
(83%)
16
(36%)
Move decimal (see decimal arithmetic)
-
-
Load Multiple Registers (LDM)
4
(1%)
4
(9%)
Store Multiple Registers (STM)
1
(0%)
1
(3%)
Total
439
(100%)
44
(100%)
aWe assume that this is implemented as 243 LD and 121 ST.

Table 3.17 Expected distribution (per 100 HLL operations) within Move class of instructions (systems applications) by architecture type.
L/S
R/M
R+M
Integer Load (LD)
65
(61%)
50
(57%)
14
(52%)
Integer Store (ST)
23
(21%)
18
(21%)
5
(19%)
Integer Register Move (MOVE)
13
(12%)
13
(15%)
2
(7%)
Load Multiple Registers (LDM)
4
(4%)
4
(5%)
4
(15%)
Store Multiple Registers (STM)
2
(2%)
2
(2%)
2
(7%)
Total
107
(100%)
87
(100%)
27
(100%)

 
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