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To get an idea of the distribution of the number of instructions between branches, consider Figure 3.4. The mean of 7.5 instructions would correspond to a branch frequency of about 13%, akin to our L/S scientific environment model, although the actual data (MacDougall [189]) are from a somewhat different environment. Figure 3.4 illustrates the wide variance of basic block lengths. |
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EXAMPLE 3.1 USING BRANCH DATA |
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Find the fraction of all branches that go to the target: |
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(a) For a scientific environment. |
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Refer to Table 3.10. From 3.10(a) we have: |
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| BC, BR, BCR, and BRR | 72.5% | | Loop control | 9.8% | | Procedure call | 17.7% |
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Now, using 3.10(c) and (d), and noting that all procedure calls go to the target, we have: |
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| BC, BR, BCR, and BRR | .725[.2 + .432] | (Table 3.10c) | | +Loop control | .098[.91] | (Table 3.10d) | | +Procedure call | .177 | | | Total | 0.724 | |
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(b) Repeat for a systems environment. |
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Now only the type 1 branch is changed, so: |
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| BC, BR, BCR, and BRR | .725[.35 + .325] | | +Loop control | .098[.91] | | +Procedure call | .177 | | Total | 0.756 |
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(c) What fraction of branches use an AG stage? Assume that all loop control branches use an AG. |
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Now we have (Table 3.10): |
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| BC, BR | .725[.826] | (Table 3.10b) | | Loop control | .098 | | | Procedure call (BAL) | .177[.8] | (Table 3.10d) | | Total | 0.729 | |
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3.4.3 Branch Target Distribution |
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One approach to minimizing the problem of branch instructions is to provide a small, high-speed buffer managed by the instruction fetch stage of a pipelined processor (Figure 3.5) that would contain a set of sequential |
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