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Figure 3.3
Possible delay allocation in program
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Multiple instructions can be concurrently executed and still produce the correct sequential answer so long as there are no "surprises" in the instruction sequence. For a high-speed processor with instruction execution concurrency, a "surprisesrdquo; is some sort of dependency where one instruction uses the result of a previous one, or a particular instruction in the sequence is a branch instruction directing execution of a target instruction out of the sequence line. The effect of such "surprises" is to "break'' the flow of information in a pipeline processor. |
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Terms such as "pipeline breaks" and "dependencies" generally are used synonymously. |
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mean instruction sequence length is 7.5 instructions (all environments), but note that 70% of the sequences are seven instructions or fewer. The variance over user environments was not significant; the mean varied from 5.18 to 8.33. Sequences of one instruction (8%) represent a taken branch followed by a taken branch. With many short runs, it is easy to understand the importance of a short branch resolution delay. |
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Branch instructions are a very important consideration in the design of a pipelined processor. They tend to disrupt the natural flow of instructions through the pipeline by reducing the processor's ability to prefetch the instructions that it needs. There is no easy way to avoid these effects, since, as Tables 3.43.6 illustrate, they represent a significant fraction of the instructions executed no matter what the workload. |
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While the overall occurrence of branches varies from one application in an environment to another, the profile of branches remains generally constant. Between 70 and 80% of all branches are branch-on-condition, and about 10% are loop control (Table 3.10a). The remaining instructions are procedure call. Among these classes, the most variable is procedure call. |
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