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Figure 2.45
Register set architectures. |
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Registers may be organized in many different ways: |
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1. As a conventional single register set (SRS). |
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2. As multiple or windowed register sets (MRS). |
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3. As a stack cache buffer or a contour buffer. |
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Even a few registers, however organized, go a long way in reducing the memory traffic. For example, an all-memory three-address architecture has about twice the data traffic of a simple stack-based architecture. In fact, as few as three registers in a register set architecture can play the role of a stack in capturing temporary values that are used within expressions, resulting in about the same data traffic that would have been realized with the stack architecture. Of course, temporary storage is only part of the picture, as registers play valuable functions in maintaining addresses for indices and in maintaining pointers to various control and data functions. |
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Suppose that all architectures of interest consist of at least eight registers, whether explicitly available for programmer use or implicitly designated for various functions; this number is sufficient to capture most temporary values that are used within statements (Figure 2.45). Additional registers can be used to reduce data traffic from statement to statement. We define the eight-register processor as a baseline processor or as unity data traffic [206] (Figure 2.46). Additional registers improve the data traffic; however, it is not simply the number of registers but the kind of organization and algorithms surrounding the registers that make the difference in the resulting data traffic. |
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Registers (and data buffers) hold values that are usable within a cycle (Figure 2.47). They generally are multiported and allow the access of two source variables and the storage of the result in the same cycle. The "register-to-register ADD" or similar basic ALU operation is one of several paths critical to determining the cycle time. The larger the register set, the more difficult it is to maintain rapid access and hence fast cycle times. On the other hand, the larger the buffer available to the processor, the lower the memory traffic demand on the memory system. The number of buffer entries and the way they are used determine the data traffic to memory. |
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Before describing multiple register sets, consider the topic of buffering data. It is common practice in modern systems to assign data variables relative to a run-time stack in memory (Figure 2.48). Global variables (or |
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